1. Field of the Invention
The invention relates generally to a method of manufacturing a flash memory device, and more particularly to, a method of manufacturing a flash memory device using a shallow trench isolation (STI) process and a self-aligned source (SAS) etch process.
2. Description of the Prior Art
Generally, a common source line of a flash EEPROM is formed by means of a tungsten local interconnection (WLI) process or a self-aligned source (SAS) etch process. It is considered that the tungsten local interconnection (WLI) process is inadequate in applying it to higher-integrated devices since a contact margin must be considered. The self-aligned source etch process is thus widely used in order to realize higher-integration of the device.
In the method of manufacturing the flash memory device using the self-aligned source etch process, the common source line is formed by the self-aligned etch process for removing a cell isolation film existing between sources of an unit cell and an impurity ion implantation process for connecting neighboring sources. The cell isolation film may be formed by various methods. However, in order to increase the level of integration in the semiconductor device, the cell isolation film is recently formed by a shallow trench isolation (STI) process. A conventional method of manufacturing the flash memory device using the shallow trench isolation process and the self-aligned source etch process will be below described.
FIG. 1 is a layout diagram of the flash memory cell for explaining the conventional method of manufacturing the flash memory device, FIG. 2A through FIG. 2D are cross sectional views of the flash memory devices taken along line 2-2xe2x80x2 in FIG. 1, FIG. 3A through FIG. 3D are cross sectional views of the flash memory devices taken along line 3-3xe2x80x2 in FIG. 1, and FIG. 4A through FIG. 4D are cross sectional views of the flash memory devices taken along line 4-4xe2x80x2 in FIG. 1.
Referring now to FIG. 1, FIG. 2A, FIG. 3A and FIG. 4A, a pad oxide film 12 and a pad nitride film 14 are sequentially formed on a semiconductor substrate 10 and are then patterned. A plurality of straight trenches 16 are formed in the semiconductor substrate 10 through the shallow trench isolation (STI) process using the patterned pad oxide film 12 and the pad nitride film 14 as an etch mask. After a wall oxidation process is performed, a gap fill oxide film 18 is formed so that the plurality of the straight trenches 16 are sufficiently buried.
By reference to FIG. 1, FIG. 2B, FIG. 3B and FIG. 4B, the gap fill oxide film 18 is planarized by means of a chemical mechanical polishing (CMP) process until the pad nitride film 14 is exposed. The planarized pad nitride film 14 and the pad oxide film 12 are removed to leave the gap fill oxide film 18 only at the straight trenches, so that a plurality of the straight cell isolation films 18T are formed. As the straight cell isolation films 18T are formed, a plurality of active regions are defined in the same direction to the straight cell isolation films 18T. After an ion implantation process for controlling the threshold voltage is performed, tunnel oxide films 20 are formed on the semiconductor substrate 10 in the active regions. Conductive layers 22 for the floating gate are then formed on the entire structure on which the tunnel oxide films 20 are formed. Next, the conductive layers 22 for the floating gate are patterned by means of an etch process using the floating gate mask.
Referring to FIG. 1, FIG. 2C, FIG. 3C and FIG. 4C, a dielectric film 24, a conductive layer 26 for a control gate, and a hard mask layer 28 are sequentially formed on the entire structure including the patterned conductive layers 22 for the floating gate. The conductive layers 26 for the control gate are then patterned by an etch process using a mask for the control gate, so that a plurality of control gates 26G being the word lines are formed in a direction intersecting the straight cell isolation films 18T. Next, the exposed portions of the patterned conductive layers 22 for the floating gate are etched by the self-aligned etch process. Thereby, a plurality of floating gates 22G each of which exists every unit cell while overlapping with the control gates 26G, respectively, are formed.
Referring to FIG. 1, FIG. 2D, FIG. 3D and FIG. 4D, the exposed portions of the straight cell isolation films 18T are removed by the self-aligned source etch process. Thereby, a plurality of recesses 30 are formed in the semiconductor substrate 10 as shown in FIG. 4D. An impurity ion is implanted into the exposed portions of the semiconductor substrate 10 through a cell source/drain implantation process. Thus, respective drains 32 are formed every unit cell and a common source line 34 sharing the plurality of the cells is formed.
In the cell of the flash memory device, erase or program operations are performed by injecting electrons into the floating gate through Fowler-Nordheim tunneling or hot carrier injection. In order for the cell to operate, independent word lines, bit lines, the common source line and the sub-line are necessary. In order to increase the level of integration in the semiconductor device, the cell size is shrunken by reducing the width of the line. Though the chip size is decided depending on the degree that the width of the line is reduced, the cell characteristic is degraded if the width of the line is too reduced. Thus, there is a limit in increasing the level of integration in the semiconductor device. In particular, if the common source line is formed by the shallow trench isolation (STI) process as in the conventional method, an electrical characteristic of the common source line is affected by the shape of the trench. Thus, in order to form the trench that is uniform and has an adequate shape to the common source line, the process of forming the trench is very difficult. Further, an over-etch process is necessarily required in order to completely remove oxide filled in the trench by the self-aligned source etch process. The surface of the semiconductor substrate, the tunnel oxide film, the gate, and the like are damaged due to excess over etch. Due to this, there are problems that the electrical characteristic and reliability of the flash memory device are degraded. In addition, an impurity ion is implanted into the recess from which the straight cell isolation film is removed, thus forming the common source line is formed by implanting. In this case, there is a limit in reducing the width of the common source line due to an electrical characteristic. There is a difficulty in increasing the level of integration in the device.
The present invention is contrived to solve the above problems and an object of the present invention is to provide a method of manufacturing a flash memory device that can uniformly maintain an electrical characteristic of a common source line, improve the productivity and yield of the device due to simplified process and reduce the cell size. To this end, a plurality of isolating cell isolation films are formed by a shallow trench isolation process so that active regions are defined between sources and sources in respective unit cells. Thus, trenches are not formed at a common source line portion between the isolating cell isolation films, and portions of the common source lines between the isolating cell isolation films are overlapped with word lines like the sources of the unit cell.
In detail, in order to accomplish the above object, the method of manufacturing a flash memory device according to the embodiment of the present invention, is characterized in that it comprises the steps of sequentially forming a pad oxide film and a pad nitride film on a semiconductor substrate, forming a plurality of isolating trenches in the semiconductor substrate by means of a shallow trench isolation process using the patterned pad oxide film and the pad nitride film as an etch mask, performing a wall oxidization process and then removing the pad nitride film and the pad oxide film, forming a gap fill oxide film on the entire structure of the semiconductor substrate so that the plurality of the isolating trenches are sufficiently buried, polishing and planarizing the gap fill oxide film by means of a chemical mechanical polishing process, etching a portion of the polished gap fill oxide film to form a plurality of oxide film line patterns and a plurality of isolating cell isolation films, forming tunnel oxide films and conductive layers for a floating gate at an exposed portion of the semiconductor substrate, patterning the conductive layers for the floating gate by means of an etch process using the floating gate mask, sequentially forming a dielectric film, a conductive layer for a control gate and a hard mask layer on the entire structure including the conductive layers for the floating gate, patterning the conductive layers for the control gate by means of an etch process using a mask for the control gate, thus forming a plurality of control gates, performing a self-aligned etch process to etch exposed portions of the conductive layers for the floating gate, thus forming a plurality of floating gate, and removing exposed portions of the oxide film line patterns by means of the self-aligned source etch process and then forming a plurality of drains and a plurality of common source lines by means of a cell source/drain implantation process.